Application-specific integrated circuits, or “ASICs,” are circuits designed to satisfy the requirements of a particular electronic system. In designing an ASIC, circuit configurations that perform the required function are entered into an ASIC design system using either a hardware description language (HDL) and/or a schematic entry tool. HDLs represent circuits as lines of code, while schematic entry tools represent circuits using interconnected symbols that represent simple or complex analog or logic functions. In either case, the components used to implement the circuit design are chosen from a library of ASIC cells that represent simple or complex operations. (ASIC “cells” are alternatively referred to as modules, blocks, macros, etc.) The resulting designs are typically expressed in some form of hardware description language, from which they are synthesized to produce a “netlist,” a file that contains a description of all the components and interconnections in the circuit design, or a portion of the circuit design. Netlists are conventionally stored on computer-readable media, such as magnetic tapes or computer disks.
The function and speed performance of ASIC cells, or “circuit cells,” are typically well characterized. Conventional design tools called logic and circuit simulators use custom test vectors and functional and timing information from the netlist to predict whether a circuit made in conformity with the netlist description will function correctly. Next, a place-and-route tool is employed to define the physical placement of cell instances and their interconnections on a semiconductive material, such as a semiconductor wafer or die. Wafer dicing may be employed to create individual semiconductor die.
Modern circuit designs are often far too complex to be designed by a single engineer or even a single team of engineers. Design specifications for complex circuit designs are therefore defined hierarchically as a collection of functional blocks. Rather than “reinvent the wheel” for every functional block of a given circuit design, IC manufactures often purchase intellectual-property (IP) cores that fully characterize the contents of a given functional block. An IC manufacturer might purchase IP cores that define, for example, an arithmetic logic unit, a memory array, a microcontroller, or an interface circuit, to name but a few examples. All of the blocks that define the function of a complete IC are compiled into a single netlist and are provided to another design team for placing and routing.
FIG. 1 (prior art) depicts a hypothetical floorplan of an IC 100 that includes some undescribed core logic 105, an instance of a reference clock cell 110, and a plurality of serializer/deserializer (SerDes) cell instances 115A-115D. For the sake of brevity, most of the routing is not shown, but a clock path 122 from an output port 120 of reference clock cell 110 extends directly to the respective clock input ports 123 of SerDes cell instances 115A and 115B, and by way of a clock buffer 125 to the respective clock input ports 123 of SerDes cell instances 115C and 115D. Clock path 122 and reference buffer 125 are part of the general routing, and are physically outside the boundaries of instances 110 and 115A-D.
FIG. 1 is illustrative; in practice, intra-block routing is vastly more complex. Not only are there a great many signal paths to define on a limited area, but the signal paths must often be manipulated by hand to solve timing problems and to improve circuit performance. This is particularly true in the example given in which the routed signal is a high-speed reference clock that must be delivered to each SerDes cell instance 115A-115D with minimal phase noise. Routing is therefore an iterative process of routing, simulating, troubleshooting, and rerouting. To make matters worse, the type and criticality of routing often depends upon the needs of particular cells, the contents of which may not be understood by those charged with placing and routing instances of those cells. In the example of FIG. 1, SerDes cell instances 115A-115D are exceptionally high-speed input/output circuits that require high-speed differential clock signals and that are very sensitive to phase noise. Customers less familiar with the needs of such cells and the design of high-speed clocking infrastructure are understandably concerned about meeting the clocking requirements of sensitive, high performance circuits.
In a particular example, Rambus Inc. of Los Altos, Calif., designs SerDes cells implemented as “quads” with one, two, or four phase-locked loops (PLLs) or multiplying delay-locked loops (MDLLs) and associated interpolator clock and data recovery (CDR) circuitry to support the operation of SerDes lanes. In the depicted example, SerDes cell instances 115A-115Ds require input reference clock signals IntClk for use by PLL 130 in generating high-speed transmit and receive clock signals (not shown). The routing of these reference clock signals from the circuit board on which the ASIC is placed or attached, optionally through reference buffer cell 125, to one or more cell instances has been very complicated and application specific. Both Rambus and their customers have been concerned about how the reference clocks are buffered, what power supplies are used for the buffers, and how the reference clocks are shared throughout the chip. A simplified and more robust approach is needed for reliable reference clock routing.